Download driver DCSD Status LED

This direct execution saves precious time during the startup of system This is done with non linear interface , which will further be described below with reference to the flow chart of FIG.

The microprocessor is initialized in step after a system reset signal is received by either processor or interface This type of triggering reset can be either a hard or a soft reset.

In step the microprocessor executes boot loader seen in FIGS. As previously mentioned, in the example of system implementing NAND memory, boot loader comprises instructions within the first page of the NAND memory. The instructions follow each other in a sequential manner. That is to say, that the first instruction to be executed has an address in the first area to be read and the second instruction to be executed has an address in the second area, contiguous to the first area, and so on.

This is important because in NAND flash memory, and in other non linear memory, one area, byte for example, cannot be read without first reading all the other area before it the first bytes. The critical registers of the microprocessor are set up in step A. This comprises disabling the interrupts of the microprocessor, defining the location of the destination memory, and initializing the destination memory. The destination in the example of system is RAM The destination memory may be one or more individual RAM chips, may be within processor , or may be any type of memory located elsewhere within the smart device that is being booted.

The registers of the microprocessor are set as follows for an 8 bit system incorporating NAND flash memory as the non linear storage device. Transferring reading or writing bytes of data in the NAND memory used to illustrate the operation of NLSD is a complicated process comprising multiple operations that must be precisely timed. The data is then put out on data bus and goes to NLI where it is intern transferred again over data bus to microprocessor Interface calculates the location address of the byte within the page.

This address is divided into a minimum of three bytes. For a Mbit device, four bytes must be read. Interface selects from one of three commands First , Second , or spare area.

Interface writes the command in step 2 to the NLSD as follows:. Interface then sends the address as follows:. Referring again to FIG. When these instructions are read and executed by the microprocessor directly from NLSD , they will then copy the boot code to RAM in step B.

In step , the microprocessor executes the copied portion of boot code from RAM The present invention has several advantages. The interface can use a very low cost programmable logic device, ASIC, or may be incorporated into the processor in a system on chip design.

The system was designed to have the maximum possible access speed, therefore minimizing the startup time of any device incorporating the system or method of the present invention. It provides a simple register based access model to make the system easy to use and incorporate by programmers.

It also supports different system configurations and platforms. For example, 8, 16, 32 or other bit systems can be supported. While embodiments of the present invention have been shown and described, changes and modifications to these illustrative embodiments can be made without departing from the present invention in its broader aspects. Thus, it should be evident that there are other embodiments of this invention which, while not expressly described above, are within the scope of the present invention and therefore that the scope of the invention is not limited merely to the illustrative embodiments presented.

Therefore, it will be understood that the appended claims set out the metes and bounds of the invention. However, as words are an imperfect way of describing the scope of the invention, it should also be understood that equivalent structures and methods while not within the express words of the claims are also within the true scope of the invention. A method for booting a microprocessor controlled device including a non linear storage device, the method comprising: receiving a system reset signal;.

The method of claim 1 wherein the first portion of the system boot code is executed by the microprocessor without first copying the first portion of the system boot code into RAM. The method of claim 1 wherein the portion of the system boot code residing in the non linear storage device executed by the microprocessor is bytes or less.

The method of claim 1. The method of claim 1 further comprising: copying a second portion of system boot code from the non linear storage device into RAM;. The method of claim 6 wherein executing a first portion of the system boot code residing in the non linear storage device with the microprocessor further comprises: receiving data from the non linear memory after the pulse; and.

A microprocessor based system comprising: a microprocessor operable to read linear memory devices;. The processor will sequentially specify linear addresses from which to read. In a typical memory system, the protocol to transfer data from the memory to the host is as follows: 1 select the memory device by asserting the chip select line; 2 select the address from which to read by asserting the address of the address bus; 3 assert the read signal.

The memory device will respond with the data asserted on the data bus. A typical program contains instruction data that are stored in various different areas of the memory that are not contiguous or adjacent.

Thus, in executing a program, the processor may first execute an instruction from an address in one area and then execute an address from a second and third etc.

Furthermore, there is no standard dictating a logical order in which the areas are read or executed from. Each program may execute from different areas according to its own particular routines. However, some types of storage devices such as flash memory, specifically NAND and AND type flash memory, are not linearly addressable.

This means that the processor cannot read or execute code from them upon bootup. The storage space in NAND memory is broken up into discrete groups of data referred to as pages.

In order to retrieve the data, the page must first be specified, then the location of the data on the page, specified as an offset from the beginning of the page, must also be specified.

However, unlike in linear storage devices, if a page is, for example, bytes in length, byte number cannot be read without first reading the preceding bytes. Furthermore, reading just one byte is a relatively more complicated procedure that does not follow the typical timing requirements of linear memory.

The system and method of booting from a non linear storage device has many applications in the startup of electronic devices that employ non linear storage devices. It can be used to boot up any microprocessor controlled device, such as but not limited to cellular phones, portable organizers, computers, global positioning systems, and smart appliances. Waiting for a device to boot-up is extremely frustrating, whether it be a cellular phone, a computer, portable organizer, or any other smart device.

The time required for the boot code to start executing with the present invention is significantly faster than in prior devices that relied on shadowing of the boot code before execution. The cost of devices made in accordance with the present invention is also reduced compared to devices using a dedicated code storage device to store the boot code. A first aspect of the invention is a method for booting a microprocessor controlled device including a non linear storage device.

The method comprises receiving a system reset signal and initializing the non linear storage device such that the non linear storage device points to system boot code within the non linear storage device. It further comprises executing a first portion of the system boot code from the non linear storage device with the microprocessor. A second aspect of the invention is a microprocessor controlled device comprising a microprocessor, volatile RAM, a non linear memory, and a linear memory emulator operable to translate code in the non linear memory into a linear format for execution by the microprocessor.

Another aspect of the invention is a microprocessor based system comprising a microprocessor operable to read linear storage devices, a non linear storage device, and means for executing code on the non linear storage device with the microprocessor operable to read linear storage devices. The following is a detailed description of illustrative embodiments of the present invention.

As these embodiments of the present invention are described with reference to the aforementioned drawings, various modifications or adaptations of the methods and or specific structures described may become apparent to those skilled in the art. All such modifications, adaptations, or variations that rely upon the teachings of the present invention, and through which these teachings have advanced the art, are considered to be within the scope of the present invention.

Hence, these descriptions and drawings are not to be considered in a limiting sense, as it is understood that the present invention is in no way limited to the embodiments illustrated.

While the system and method of the present invention encompasses startup of any device incorporating any type of non linear storage device, for purposes of illustrating the invention, NAND flash memory will be described. Booting from non-linear memory has many advantages over booting from a dedicated code storage device such as ROM. It also has advantages over having to first copy or shadow a copy of code into RAM memory before the CPU can execute it.

In the case that the DCSD has already been eliminated, but the device must first copy the boot instructions into RAM in order for the microprocessor or CPU to execute the instructions and start the device, the startup time is significantly reduced with the present invention. The present invention works with virtually any processor and is more compatible with a larger variety of processors than systems that utilize a DCSD. The time required for the boot code to start executing with the present invention is approximately the access time of the non linear storage device.

In the NAND example, this is approximately 15 microseconds, whereas shadowing takes several hundred milliseconds before execution may even begin in past systems.

The source code on CD ROM also forms part of this description and is hereby incorporated by this reference in its entirety. Processor is connected via system bus to a number of other devices. System bus is connected to non linear storage device NLSD , non linear storage device interface NLI , processor , volatile random access memory RAM , peripherals , and human interface devices NLI comprises a programmable logic device or application specific integrated circuit or logic gates incorporated into a chip sometimes described as a system in a chip.

It also comprises the logic implemented in the aforementioned devices. Peripherals can be printers or other output devices as well as additional drives and any other peripherals that are well known in the art. Human interface devices are things such as a keyboard, monitor, mouse, microphone or speakers and are likewise well known in the art. As the present invention will be especially advantageous with portable devices such as cellular telephones, the peripherals and human interface devices may all be integrated in one package, however they may also be traditional individual components.

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